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em có 1 đoạn chương trình viết bằng VHDL.em test thử báo lỗi thế này em không hiểu thế nào mong các bác giúp em.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 29. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 37. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 39. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 42. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 44. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 47. Wait for statement unsupported.
Em không biết đính kèm file thế nào nên em gửi luôn chương trình các bác xem.Em mới học về cái này được ít ngày mong các bác chỉ giáo
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.numeric_bit.all;
entity test_nhan4bit is
end test_nhan4bit;
architecture test of test_nhan4bit is
component nhan4bit is
port (
in1: in std_logic_vector(3 downto 0);
in2: in std_logic_vector(3 downto 0);
clk: in std_logic;
reset: in std_logic;
we: in std_logic;
ketqua: out std_logic_vector(7 downto 0)
);
end component;
signal in1: std_logic_vector(3 downto 0);
signal in2:std_logic_vector(3 downto 0);
signal clk: std_logic :='0';
signal reset: std_logic;
signal we: std_logic;
signal ketqua: std_logic_vector(7 downto 0);
begin
create_clock: process
begin
wait for 2 ns;
CLK <= not CLK after 50 ns;
end process create_clock;
-- create test data
create_data: process
begin
in1 <= "1001"; in2 <= "1100";
reset <= '0'; WE <= '0';
wait for 150 ns;
reset <= '1';
wait for 170 ns;
reset <= '0';
WE <= '1';
wait for 150 ns;
WE <= '0';
wait for 1400 ns;
in1 <= "1011"; in2 <= "1000";
WE <= '1';
wait for 150 ns;
WE <= '0';
wait;
end process create_data;
dut: component nhan4bit
port map(clk =>clk, reset =>reset, we =>we, in1=>in1, in2 => in2, ketqua=>ketqua);
end test;
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 29. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 37. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 39. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 42. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 44. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/THANHLONG/Desktop/nhan4bit/nhan4bit/test_nhan4bit.vhd" Line 47. Wait for statement unsupported.
Em không biết đính kèm file thế nào nên em gửi luôn chương trình các bác xem.Em mới học về cái này được ít ngày mong các bác chỉ giáo
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.numeric_bit.all;
entity test_nhan4bit is
end test_nhan4bit;
architecture test of test_nhan4bit is
component nhan4bit is
port (
in1: in std_logic_vector(3 downto 0);
in2: in std_logic_vector(3 downto 0);
clk: in std_logic;
reset: in std_logic;
we: in std_logic;
ketqua: out std_logic_vector(7 downto 0)
);
end component;
signal in1: std_logic_vector(3 downto 0);
signal in2:std_logic_vector(3 downto 0);
signal clk: std_logic :='0';
signal reset: std_logic;
signal we: std_logic;
signal ketqua: std_logic_vector(7 downto 0);
begin
create_clock: process
begin
wait for 2 ns;
CLK <= not CLK after 50 ns;
end process create_clock;
-- create test data
create_data: process
begin
in1 <= "1001"; in2 <= "1100";
reset <= '0'; WE <= '0';
wait for 150 ns;
reset <= '1';
wait for 170 ns;
reset <= '0';
WE <= '1';
wait for 150 ns;
WE <= '0';
wait for 1400 ns;
in1 <= "1011"; in2 <= "1000";
WE <= '1';
wait for 150 ns;
WE <= '0';
wait;
end process create_data;
dut: component nhan4bit
port map(clk =>clk, reset =>reset, we =>we, in1=>in1, in2 => in2, ketqua=>ketqua);
end test;
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