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Em đang làm đồ án tốt nghiệp mà mắc đoạn code này quá. Khônh hiểu người ta sử dụng như thế nào.
còn đây là một đoạn nữa họ hiển thị mấy chữ như: F1-Stop Game, F2 - NEW GAME, A - MOVE LEFT, D - MOVE RIGHT, SPACE - ROTATE...
Ai hiểu đoạn code này thì chỉ bảo giùm em nhé. Giải thích rõ ràng một chút nhe.
Giải thích cho em vì sao nó lại có những con số này và ý nghĩa của nó
Liên hê email: nguyentrongvinh79@gmail.com
Em cảm ơn nhiều
Code:
-- first BlockRAM
RAMB4_S8_inst2 : RAMB4_S8
generic map (
-- 03 0 02 0 01 0 00 0
INIT_00 => X"FF80808080808080FF0101010101010180808080808080FF0000000000000000",
-- 07 0 06 0 05 0 04 0
INIT_01 => X"80808080808080800101010101010101FF0000000000000000000000000000FF",
-- 0B 0 0A 0 09 0 08 0
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 0F 0 0E 0 0D 0 0C 0
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 13 0 12 0 11 0 10 0
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 17 0 16 0 15 0 14 0
INIT_05 => X"0000000000000000003810101010301000344854444444380000000000000000",
-- 1B 0 1A 0 19 0 18 0
INIT_06 => X"007804043840403C007C40201008047C00000000000000000000000000000000",
-- 1F 0 1E 0 1D 0 1C 0
INIT_07 => X"0000000000000000003C20100804443800285454544444440044447C44444438",
-- 23 0 22 0 21 0 20 0
INIT_08 => X"0070484444444870004444281028444400384440404044380000000000000000",
-- 27 0 26 0 25 0 24 0
INIT_09 => X"0000000000000000003844040810083C0008087C48281808007C40407840407C",
-- 2B 0 2A 0 29 0 28 0
INIT_0A => X"004040407840407C001028444444444400000000000000000000000000000000",
-- 2F 0 2E 0 2D 0 2C 0
INIT_0B => X"0000000000000000003844040478407C0044485078444478001010101010107C",
-- 33 0 32 0 31 0 30 0
INIT_0C => X"004444447C44444400784444784444780000444C546444440000000000000000",
-- 37 0 36 0 35 0 34 0
INIT_0D => X"000000000000000000384444784020180010101028444444003844445C404438",
-- 3B 0 3A 0 39 0 38 0
INIT_0E => X"003028080808081C0044444444546C4400000000000000000000000000000000",
-- 3F 0 3E 0 3D 0 3C 0
INIT_0F => X"00000000000000000038444438444438002020201008047C0038444444444444")
port map (
DO => cp0, -- 8-bit data output
ADDR => ADDR, -- 9-bit address input
CLK => clkd, -- Clock input
DI => "00000000", -- 8-bit data input
EN =>'1', -- RAM enable input
RST => '0', -- Synchronous reset input
WE => '0' -- RAM write enable input
);
-- second BlockRAM
RAMB4_S8_inst1 : RAMB4_S8
generic map (
-- 43 0 42 0 41 0 40 0
INIT_00 => X"0038101010101038004448506050484400000000000000000000000000000000",
-- 47 0 46 0 45 0 44 0
INIT_01 => X"0000000000000000003008043844443800384464544C44380038444444444438",
-- 4B 0 4A 0 49 0 48 0
INIT_02 => X"007C404040404040000000000000000000000000000000000000000000000000",
-- 4F 0 4E 0 4D 0 4C 0
INIT_03 => X"0000000000000000000000007C00000000404040784444780000000000000000",
-- 53 0 52 0 51 0 50 0
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 57 0 56 0 55 0 54 0
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 5B 0 5A 0 59 0 58 0
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 5F 0 5E 0 5D 0 5C 0
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 63 0 62 0 61 0 60 0
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 67 0 66 0 65 0 64 0
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 6B 0 6A 0 69 0 68 0
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 6F 0 6E 0 6D 0 6C 0
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 73 0 72 0 71 0 70 0
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 77 0 76 0 75 0 74 0
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 7B 0 7A 0 79 0 78 0
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 7F 0 7E 0 7D 0 7C 0
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => cp1, -- 8-bit data output
ADDR => ADDR, -- 9-bit address input
CLK => clkd, -- Clock input
DI => "00000000", -- 8-bit data input
EN =>'1', -- RAM enable input
RST => '0', -- Synchronous reset input
WE => '0' -- RAM write enable input
);
Code:
RAMB4_S4_S4_inst : RAMB4_S4_S4
generic map (
-- 1 0
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 3 2
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 5 4
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- 7 6
INIT_03 => X"00000000000000000000000000EEEC00000000000000000000000000000CCCCC",
-- 9 8
INIT_04 => X"0000000000000000000000000AEEEC0000000000000000000000000AAAAAEC00",
-- 11 10
INIT_05 => X"0000000000000000000000000AEEE0DD0000000000000000000000000A00EC00",
-- 13 12
INIT_06 => X"0000000000000000000000F0000F00DD0000000000000000000000000A000D0D",
-- 15 14
INIT_07 => X"00000000000000000000000F0F09D00D0000000000000000000000F000F90D0D",
-- 17 16
INIT_08 => X"00000000000000000000000F0F090000000000000000000000000000F0090000",
-- 19 18
INIT_09 => X"0000000000000000000000F0000F00000000000000000000000000F000F90000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => DOA, -- Port A 4-bit data output
DOB => DOB, -- Port B 4-bit data output
ADDRA => ADDRA, -- Port A 10-bit address input
ADDRB => ADDRB, -- Port B 10-bit address input
CLKA => mclk, -- Port A clock input
CLKB => mclk, -- Port B clock input
DIA => DIA, -- Port A 4-bit data input
DIB => "0000", -- Port B 4-bit data input
ENA => '1', -- Port A RAM enable input
ENB => '1', -- Port B RAM enable input
RSTA => '0', -- Port A Synchronous reset input
RSTB => '0', -- Port B Synchronous reset input
WEA => WEA, -- Port A RAM write enable input
WEB => '0' -- Port B RAM write enable input
);
--------------------------------------------------------------------
--textbox's BlockRAM
RAMB4_S8_S8_inst : RAMB4_S8_S8
generic map (
INIT_00 => X"0007040404040404040404040404040404040404040404040404040404040401",
-- F1 - STOP GAME
INIT_01 => X"0007000000000000000000000000000000243A1C34004D442C1B004E00162B07",
-- F2 - NEW GAME
INIT_02 => X"000700000000000000000000000000000000243A1C34001D2431004E001E2B07",
-- A - MOVE LEFT
INIT_03 => X"0007000000000000000000000000000000002C2B244B00242A443A004E001C07",
-- D - MOVE RIGHT
INIT_04 => X"00070000000000000000000000000000002C3334432D00242A443A004E002307",
-- SPACE - ROTATE
INIT_05 => X"0007000000000000000000000000000000242C1C2C442D004E0024211C4D1B07",
-- S - SPEED
INIT_06 => X"000700000000000000000000000000000000000000002324244D1B004E001B07",
-- TOP SCORE
INIT_07 => X"00070000000000000000000000000000000000000000242D44211B004D442C07",
-- YOUR SCORE
INIT_08 => X"000700000000000000000000000000000000000000242D44211B002D3C443507",
INIT_09 => X"0007000000000000000000000000000000000000000000000000000000000007",
INIT_0A => X"0007000000000000000000000000000000000000000000000000000000000007",
INIT_0B => X"0007000000000000000000000000000000000000000000000000000000000007",
INIT_0C => X"0007000000000000000000000000000000000000000000000000000000000007",
INIT_0D => X"0007000000000000000000000000000000000000000000000000000000000007",
INIT_0E => X"0007000000000000000000000000000000000000000000000000000000000007",
INIT_0F => X"0007050505050505050505050505050505050505050505050505050505050503")
port map (
DOA => DOAt, -- Port A 8-bit data output
DOB => DOBt, -- Port B 8-bit data output
ADDRA => ADDRAt, -- Port A 9-bit address input
ADDRB => ADDRBt, -- Port B 9-bit address input
CLKA => mclk, -- Port A clock input
CLKB => clkdiv, -- Port B clock input
DIA => DIAt, -- Port A 8-bit data input
DIB => "00000000", -- Port B 8-bit data input
ENA => '1', -- Port A RAM enable input
ENB => '1', -- Port B RAM enable input
RSTA => '0', -- Port A Synchronous reset input
RSTB => '0', -- Port B Synchronous reset input
WEA => WEAt, -- Port A RAM write enable input
WEB => '0' -- Port B RAM write enable input
);
Giải thích cho em vì sao nó lại có những con số này và ý nghĩa của nó
Liên hê email: nguyentrongvinh79@gmail.com
Em cảm ơn nhiều
