Em có bài này chưa biết làm, các anh chỉ giúp em nha ^^.
Bài này là part5 trong lab 7 của VHDL, chắc nhiều anh làm qua rồi. Các anh vui lòng chỉ dẫn cho em với
(Càng cụ thể từng bước càng tốt các anh ạ
)
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Part V - lab 7
For this part you are to design a circuit for the DE2 board that scrolls the
word "HELLO" in ticker-tape fashion on the eight 7-segment displays HEX7 − 0.
The letters should move from right to left each time you apply a manual clock
pulse to the circuit. After the word "HELLO" scrolls off the left side of the
displays it then starts again on the right side.
Design your circuit by using eight 7-bit registers connected in a queue-like
fashion, such that the outputs of the first register feed the inputs of the
second, the second feeds the third, and so on. This type of connection
between registers is often called a pipeline. Each register’s outputs should
directly drive the seven segments of one display. You are to design a finite
state machine that controls the pipeline in two ways:
1. For the first eight clock pulses after the system is reset, the FSM inserts
the correct characters (H,E,L,L,0, , , ) into the first of the 7-bit registers in
the pipeline.
2. After step 1 is complete, the FSM configures the pipeline into a loop that
connects the last register back to the first one, so that the letters continue
to scroll indefinitely.
Write VHDL code for the ticker-tape circuit and create a Quartus II project
for your design. Use KEY 0 on the DE2 board to clock the FSM and pipeline
registers and use SW 0 as a synchronous active-low reset input. Write VHDL
code in the style shown in Figure 3 for your finite state machine.
Compile your VHDL code, download it onto the DE2 board and test the circuit.
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