viet stack bang VHDL

[neo]

minh viet controll stack duoi dang hanh vi tren ngon ngu VHDL nhung thay ruom ra qua, ban nao co cach viet hay cho minh tham khao voi. THank!
Đây là đoạn code của mình:

entity ctr_stack is
Port ( clk,rst : in std_logic;
push,pop : in std_logic;
full,empty : out std_logic;
mem_addr : out std_logic_vector(2 downto 0));

end stack;

architecture Behavioral of ctr_stack is
constant N : integer := 3;
constant top_stk: unsigned(N-1 downto 0):= "111";
constant bottom_stk: unsigned(N-1 downto 0):= "000";
signal stk_ptr_reg,stk_ptr_reg1,stk_ptr_next : unsigned(N-1 downto 0);
signal empty_flag,full_flag : std_logic;
begin
process(clk,rst)
begin
if rst ='1' then
stk_ptr_reg <=bottom_stk;
stk_ptr_reg1 <=bottom_stk;

elsif clk'event and clk='1' then
stk_ptr_reg<= stk_ptr_next;
stk_ptr_reg1 <=stk_ptr_reg;

end if;
end process;

stk_ptr_next <= stk_ptr_reg + 1 when push='1' and full_flag='0' and stk_ptr_reg/=top_stk else
stk_ptr_reg - 1 when pop='1' and empty_flag='0'and stk_ptr_reg/=bottom_stk else
stk_ptr_reg;

full_flag <= '1' when stk_ptr_reg1 = top_stk else
'0';
empty_flag<= '1' when stk_ptr_reg1= bottom_stk else
'0';

mem_addr <= std_logic_vector(stk_ptr_reg1(N-1 downto 0)) ;

empty <= empty_flag;
full <= full_flag;
end Behavioral;