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Giúp mình sửa lỗi khi gán tín hiệu giữa 2 entity khác nhau, ngôn ngữ VHDL
Mình đang code 2 block. Và mình muốn gán tín hiệu giữa 2 block này (2 entity trong VHDL) nhưng nó báo lỗi xảy ra chỗ lệnh gán (w_data.entity work.fifo_8x32) <= Mdata; như dưới đây chưa biết sửa thế nào, bác nào biết chỉ mình với, thanks.
Lỗi:
# Model Technology ModelSim SE vcom 6.5b Compiler 2009.05 May 21 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity fifo_8x32
# -- Compiling architecture enlarged_bin_arch of fifo_8x32
# -- Compiling architecture beh_arch of fifo_8x32
# -- Loading entity fifo_8x32
# -- Compiling entity controlfifo
# -- Compiling architecture controlfifo_arch of controlfifo
# ** Error: ControlFIFO.vhd(111): near "entity": expecting "CHARACTER" or "STRING" or "IDENTIFIER" or "ALL"
# ** Error: ControlFIFO.vhd(117): VHDL Compiler exiting
# D:/VHDL implementation/win32/vcom failed.
Code:
Lỗi:
# Model Technology ModelSim SE vcom 6.5b Compiler 2009.05 May 21 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity fifo_8x32
# -- Compiling architecture enlarged_bin_arch of fifo_8x32
# -- Compiling architecture beh_arch of fifo_8x32
# -- Loading entity fifo_8x32
# -- Compiling entity controlfifo
# -- Compiling architecture controlfifo_arch of controlfifo
# ** Error: ControlFIFO.vhd(111): near "entity": expecting "CHARACTER" or "STRING" or "IDENTIFIER" or "ALL"
# ** Error: ControlFIFO.vhd(117): VHDL Compiler exiting
# D:/VHDL implementation/win32/vcom failed.
Code:
Code:
-- Control FIFO Block
-- FIFO buffer 8x32
-- Synchronous FIFO buffer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity for FIFO buffer 8x34
entity fifo_8x32 is
port(
clk, reset: in std_logic;
-- FIFO controller
wr, rd: in std_logic;
full, empty: out std_logic;
-- FIFO register file
wr_en: in std_logic;
w_data: inout std_logic_vector(31 downto 0);
r_data: out std_logic_vector(31 downto 0);
-- Address signal: 2**N = Number of words, N=3
w_addr, r_addr: inout std_logic_vector(2 downto 0)
);
end fifo_8x32;
architecture enlarged_bin_arch of fifo_8x32 is
constant N: natural:=3;
signal w_ptr_reg, w_ptr_next: unsigned(N downto 0);
signal r_ptr_reg, r_ptr_next: unsigned(N downto 0);
signal full_flag, empty_flag: std_logic;
begin
-- Register
process(clk,reset)
begin
if (reset='1') then
w_ptr_reg <= (others=>'0'); -- w_ptr_reg<='00';
r_ptr_reg <= (others=>'0'); -- r_ptr_reg<='00';
elsif (clk'event and clk='1') then
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
end if;
end process;
-- Write pointer next-stage logic
w_ptr_next <=
w_ptr_reg+1 when (wr='1' and full_flag='0') else
w_ptr_reg;
full_flag <=
'1' when (r_ptr_reg(N)/=w_ptr_reg(N)and
r_ptr_reg(N-1 downto 0)=w_ptr_reg(N-1 downto 0))
else
'0';
-- Write port output
w_addr <= std_logic_vector(w_ptr_reg(N-1 downto 0));
full<= full_flag;
-- Read pointer next-stage logic
r_ptr_next <=
r_ptr_reg+1 when (rd='1' and empty_flag='0') else
r_ptr_reg;
empty_flag <= '1' when r_ptr_reg=w_ptr_reg else
'0';
-- Write port output
r_addr <= std_logic_vector(r_ptr_reg(N-1 downto 0));
empty <= empty_flag;
end enlarged_bin_arch;
architecture beh_arch of fifo_8x32 is
type reg_file_type is array (2**3-1 downto 0) of
std_logic_vector(31 downto 0);
signal array_reg: reg_file_type;
signal array_next: reg_file_type;
begin
-- Register array
process(clk,reset)
begin
if (reset='1') then
array_reg <= (others=>(others=>'0'));
elsif (clk'event and clk='1') then
array_reg <= array_next;
end if;
end process;
-- Next-state logic for register array
process(array_reg,wr_en,w_addr,w_data)
begin
array_next <= array_reg;
if wr_en='1' then
array_next(to_integer(unsigned(r_addr))) <= w_data;
end if;
end process;
-- Read port
r_data <= array_reg(to_integer(unsigned(r_addr)));
end beh_arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ControlFIFO is
port(
clk, reset: in std_logic;
MdataLast, MreqLast, full: in std_logic;
Mcmd: in std_logic_vector(2 downto 0);
MBurstLength: in std_logic_vector(7 downto 0);
ScmdAccept, wr: out std_logic);
end ControlFIFO;
architecture ControlFIFO_arch of ControlFIFO is
signal Mdata: std_logic_vector(31 downto 0);
begin
process(clk, reset)
begin
if (reset='1') then
-- default value
wr <= '0';
ScmdAccept <= '0';
elsif (clk'event and clk = '1') then
if ((Mcmd = "001" and MreqLast ='0') and MdataLast = '0') then
wr <= '1';
if (full = '0') then
(w_data.entity work.fifo_8x32) <= Mdata;
ScmdAccept <= '1';
end if;
end if;
end if;
end process;
end ControlFIFO_arch;
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