Tweet
Em đã sửa code cho đơn giản chỉ Transmit từ KIT Actel Proasic3 lên PC nhưng không hiểu sao vẫn không thể chạy đươc,bọn em sắp thi mất rồi,mong các anh bớt chút thời gian xem qua chỉ giúp em với : Nó gồm 3 module Transmit,Uart,Uart test như sau
PHP Code:
--
-- UART: transmitter
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity UARTTransmitter is
generic
(
frequency : integer;
baud : integer
);
port
(
clk : in std_logic;
txd : out std_logic;
txd_data : in std_logic_vector(7 downto 0);
txd_start : in std_logic;
txd_busy : out std_logic
);
end entity UARTTransmitter;
architecture UARTTransmitterArch of UARTTransmitter is
-- defining types
type state_type is (idle, start, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, stop1, stop2);
-- defining signals
signal state : state_type := idle; -- transmitter's state
signal data : std_logic_vector(7 downto 0);
signal baud_tick : std_logic;
signal busy : std_logic := '0';
signal baud_divider : integer range 0 to (frequency/100 + baud/100 - 1) := 0;
begin
-- assignments
txd_busy <= busy;
busy <= '0' when state = idle else '1';
-- processes
baud_gen : process(clk)
begin
if clk'event and clk = '1' then
if busy = '1' then -- trong qua trinh truyen data moi tao xung
baud_divider <= baud_divider + (baud/100);
if baud_divider > (frequency/100) then
baud_tick <= '1';
baud_divider <= 0;
else
baud_tick <= '0';
end if;
end if;
end if;
end process baud_gen;
--
state_proc : process(clk)
begin
if clk'event and clk = '1' then
case state is
when idle =>
if txd_start = '1' then -- nhan duoc tin hieu truyen
state <= start;
end if;
when start =>
if baud_tick = '1' then -- bat dau qua trinh truyen
state <= bit0;
end if;
when bit0 =>
if baud_tick = '1' then
state <= bit1;
end if;
when bit1 =>
if baud_tick = '1' then
state <= bit2;
end if;
when bit2 =>
if baud_tick = '1' then
state <= bit3;
end if;
when bit3 =>
if baud_tick = '1' then
state <= bit4;
end if;
when bit4 =>
if baud_tick = '1' then
state <= bit5;
end if;
when bit5 =>
if baud_tick = '1' then
state <= bit6;
end if;
when bit6 =>
if baud_tick = '1' then
state <= bit7;
end if;
when bit7 =>
if baud_tick = '1' then
state <= stop1;
end if;
when stop1 =>
if baud_tick = '1' then
state <= stop2;
end if;
when stop2 =>
if baud_tick = '1' then
state <= idle;
end if;
end case;
end if;
end process state_proc;
--
data_load_proc : process(clk)
begin
if clk'event and clk = '1' then
if txd_start = '1' then
data <= txd_data;
end if;
end if;
end process data_load_proc;
--
txd_proc : process(clk)
begin
if clk'event and clk = '1' then
case state is
when idle => txd <= '1';
when start => txd <= '0';
when bit0 => txd <= data(0);
when bit1 => txd <= data(1);
when bit2 => txd <= data(2);
when bit3 => txd <= data(3);
when bit4 => txd <= data(4);
when bit5 => txd <= data(5);
when bit6 => txd <= data(6);
when bit7 => txd <= data(7);
when stop1 => txd <= '1';
when stop2 => txd <= '1';
end case;
end if;
end process txd_proc;
--
-- busy_proc : process(clk)
-- begin
-- if clk'event and clk = '1' then
-- if state = idle then
-- busy <= '0'; txd_busy <= '0';
-- else
-- busy <= '1'; txd_busy <= '1';
-- end if;
-- end if;
-- end process busy_proc;
end UARTTransmitterArch;
========================================================================
========================================================================
========================================================================
--
-- UART: main entity
--
library ieee;
use ieee.std_logic_1164.all;
entity UART is
generic
(
frequency : integer;
baud : integer
);
port
(
clk : in std_logic;
--rxd : in std_logic;
txd : out std_logic;
txd_data : in std_logic_vector(7 downto 0);
txd_start : in std_logic;
txd_busy : out std_logic
--rxd_data : out std_logic_vector(7 downto 0);
--rxd_data_ready : out std_logic
);
end entity UART;
architecture UARTArch of UART is
-- defining constants
--constant OVERSAMPLING : integer := 8;
-- defining signals
-- defining components
component UARTTransmitter
generic
(
frequency : integer;
baud : integer
);
port
(
clk : in std_logic;
txd : out std_logic;
txd_data : in std_logic_vector(7 downto 0);
txd_start : in std_logic;
txd_busy : out std_logic
);
end component UARTTransmitter;
begin
-- instantiating components
TRANSMITTER : UARTTransmitter
generic map
(
frequency => frequency,
baud => baud
)
port map
(
clk => clk,
txd => txd,
txd_data => txd_data,
txd_start => txd_start,
txd_busy => txd_busy
);
end UARTArch;
========================================================================
========================================================================
========================================================================
--
-- UARTTest
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity UARTTest is
port
(
clk : in std_logic;
--rxd : in std_logic;
txd : out std_logic;
led : out std_logic
);
end entity UARTTest;
architecture UARTTestArch of UARTTest is
-- Input constants
constant CLK_FREQUENCY : integer := 40000000;
constant BAUD : integer := 115200;
constant counter : integer :=80000000;
-- defining components
component UART
generic
(
frequency : integer;
baud : integer
);
port
(
clk : in std_logic;
--rxd : in std_logic;
--rxd_data : out std_logic_vector(7 downto 0);
--rxd_data_ready : out std_logic;
txd : out std_logic;
txd_data : in std_logic_vector(7 downto 0);
txd_start : in std_logic;
txd_busy : out std_logic
);
end component UART;
-- defining signals
signal rxd_data_ready, txd_start, txd_busy : std_logic;
signal txd_data : std_logic_vector(7 downto 0);
--
type helloworld_type is (idle, h1, e1, l1, l2, o1, blank, w1, o2, r1, l3, d1, bang1, cr1);
signal state : helloworld_type := idle;
signal count:integer range 0 to counter :=0;
begin
-- instantiating components
SERIAL : UART
generic map
(
frequency => CLK_FREQUENCY,
baud => BAUD
)
port map
(
clk => clk,
--rxd => rxd,
--rxd_data => rxd_data,
--rxd_data_ready => rxd_data_ready,
txd => txd,
txd_data => txd_data,
txd_start => txd_start,
txd_busy => txd_busy
);
-- processes
state_proc : process(clk)
begin
if clk'event and clk = '1'
then
case state is
when idle =>
txd_start <= '0';
count<=count+1;
if (count = counter-1) then count<=0;
end if;
if count =0 then
txd_start <= '1';
state <= h1;
end if;
when h1 =>
if txd_busy = '0' then
txd_data <= "01001000";
state <= e1;
end if;
when e1 =>
if txd_busy = '0' then
txd_data <= "01100101";
state <= l1;
end if;
when l1 =>
if txd_busy = '0' then
txd_data <= "01101100";
state <= l2;
end if;
when l2 =>
if txd_busy = '0' then
txd_data <= "01101100";
state <= o1;
end if;
when o1 =>
if txd_busy = '0' then
txd_data <= "01101111";
state <= blank;
end if;
when blank =>
if txd_busy = '0' then
txd_data <= "00100000";
state <= w1;
end if;
when w1 =>
if txd_busy = '0' then
txd_data <= "01110111";
state <= o2;
end if;
when o2 =>
if txd_busy = '0' then
txd_data <= "01101111";
state <= r1;
end if;
when r1 =>
if txd_busy = '0' then
txd_data <= "01110010";
state <= l3;
end if;
when l3 =>
if txd_busy = '0' then
txd_data <= "01101100";
state <= d1;
end if;
when d1 =>
if txd_busy = '0' then
txd_data <= "01100100";
state <= bang1;
end if;
when bang1 =>
if txd_busy = '0' then
txd_data <= "00100001";
state <= cr1;
end if;
when cr1 =>
if txd_busy = '0' then
txd_data <= "00001101";
state <= idle;
end if;
end case;
end if;
end process state_proc;
--
-- switch_txd_proc : process(clk)
-- begin
-- if clk'event and clk = '1' then
-- if state = idle then
-- txd_start <= '0';
-- else
-- txd_start <= '1';
-- end if;
-- end if;
-- end process switch_txd_proc;
--
led_proc : process(clk)
begin
if clk'event and clk = '1' then
if state /= idle then
led <= '1';
else
led <= '0';
end if;
end if;
end process led_proc;
end architecture UARTTestArch;
...
...
Comment