FPGA Điều khiển thang máy

[Feri Rocky]

Các bác xem cho e lỗi nó báo thế này là như thế nào. e mới beginer FPGA nên ko hiểu

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.shaft;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MAIN is
    Port ( CLK : in  STD_LOGIC;
           KEEP_GOING : in  STD_LOGIC;
           START : in  STD_LOGIC;
           STOP_HERE : in  STD_LOGIC;
           F : in  STD_LOGIC_VECTOR(4 DOWNTO 0);
           HERE : in  STD_LOGIC;
           STB : in  STD_LOGIC;
           FLR : out  STD_LOGIC_VECTOR(4 DOWNTO 0);
           BRAKE : out  STD_LOGIC;
           DN : out  STD_LOGIC;
           UP : out  STD_LOGIC;
           RUN : out  STD_LOGIC;
           SLOW : out  STD_LOGIC);
end MAIN;

architecture elevator_main of MAIN is
	SIGNAL sreg : std_logic_vector (2 downto 0);
	SIGNAL next_sreg : std_logic_vector (2 downto 0);
	CONSTANT CONT_DN : std_logic_vector (2 downto 0):="010"; 
	CONSTANT CONT_UP : std_logic_vector (2 downto 0):="110";
	CONSTANT DN_FULL : std_logic_vector (2 downto 0):="011"; 
	CONSTANT DN_SLOW : std_logic_vector (2 downto 0):="001";
	CONSTANT STOP_DN : std_logic_vector (2 downto 0):="000"; 
	CONSTANT STOP_UP : std_logic_vector (2 downto 0):="100";
	CONSTANT UP_FULL : std_logic_vector (2 downto 0):="111"; 
	CONSTANT UP_SLOW : std_logic_vector (2 downto 0):="101";
	SIGNAL NR_FLR,AT_FLR : std_logic;
	
begin
FRONTEND: shaft PORT MAP (F,HERE,STB,CLK,FLR,AT_FLR,NR_FLR);
	PROCESS (CLK, next_sreg)
	Begin
			if CLK='1' ANd CLK'event Then
					sreg<= next_sreg;
			end if;
	end process;
	PROCESS (sreg,AT_FLR,KEEP_GOING,NR_FLR,START,STOP_HERE)
	begin
			BRAKE<= '0' ; DN<= '0' ; RUN<= '0'; UP<= '0';
			next_sreg <= CONT_DN;
			
			CASE sreg IS
				when CONT_DN =>
					UP <= '0';
					SLOW <= '0';
					BRAKE <= '0';
					RUN <= '1';
					DN <= '1';
					if (NR_FLR='0') Then
							next_sreg<=DN_FULL;
					else 
							next_sreg<=CONT_DN;
					end if;
				when CONT_UP =>
					SLOW<='0';
					DN<='0';
					BRAKE<='0';
					RUN<='1';
					UP<='1';
					if (NR_FLR='0') then
							next_sreg<=UP_FULL;
					else 
							next_sreg<=CONT_UP;
					end if;
				when DN_FULL=>
					up<='0';	
					SLOW<='0';
					BRAKE<='0';
					RUN<='1';
					DN<='1';
					if (NR_FLR='0') then
						next_sreg<=DN_FULL;
					end if;
					if (KEEP_GOING='0' AND nR_FLR='1') OR
							(STOP_HERE='1' AND NR_FLR='1')
							then
								next_sreg<=DN_SLOW;
					end if;
					IF (NR_FLR='1' AND STOP_HERE='0' AND KEEP_GOING='1') then
							next_sreg<=CONT_DN;
					end if;
				When DN_SLOW=>
					
					UP<='0';
					BRAKE<='0';
					RUN<='1';
					DN<='1';
					SLOW<='1';
					IF (AT_FLR='1') THEN
							NEXT_SREG<=STOP_DN;
					ELSE 
							next_sreg<=DN_SLOW;
					end if;
				when STOP_DN =>
					UP<='0';
					SLOW<='0';
					RUN<='0';
					BRAKE<='1';
					DN<='1';
					if (START='0') then
						next_sreg<=STOP_DN;
					end if;
					IF (START='1' AND KEEP_GOING='1') then
							next_sreg<=CONT_DN;
					end if;
					IF (START='1' and KEEP_GOING='0') then
							next_sreg<=STOP_UP;
					end if;
				When STOP_UP =>
					SLOW<='0';
					RUN<='0';
					DN<='0';
					BRAKE<='1';
					UP<='1';
					if (START='0') then
							next_sreg<=STOP_UP;
					end if;
					IF (START='1' And KEEP_GOING='0') then
							next_sreg<=STOP_DN;
					end if;
				When UP_FULL =>
					SLOW<='0';
					DN<='0';
					BRAKE<='0';
					RUN<='1';
					UP<='1';
					if (NR_FLR='0') then
							next_sreg<=UP_FULL;
					end if;
					IF (KEEP_GOING='0' And NR_FLR='1') or (STOP_HERE='1' and NR_FLR='1') then
							next_sreg<=UP_SLOW;
					end if;
					IF (NR_FLR='1' And STOP_HERE='0' and KEEP_GOING='1') then
							next_sreg<=CONT_UP;
					end if;
				When UP_SLOW =>
					DN<='0';
					BRAKE<='0';
					RUN<='1';
					UP<='1';
					SLOW<='1';
					if (AT_FLR='1') then
							next_sreg<=stop_UP;
					ELSE
							next_sreg<=UP_SLOW;
					end if;
				WHEN OTHERS =>
			END CASE;		
	end process;
	
end elevator_main;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shaft is
    Port ( f : in  STD_LOGIC_VECTOR(4 DOWNTO 0);
           here : in  STD_LOGIC;
           stb : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           flr : out  STD_LOGIC_VECTOR(4 DOWNTO 0);
           at_flr : out  STD_LOGIC;
           nr_flr : out  STD_LOGIC);
end shaft;

architecture shaft_logic of shaft is
Begin
	PROCESS (f,stb,clk,here)
	begin
			if (stb'event and stb='0') then
					flr<=f;
			end if;
			if (clk'event and clk='1') then
				at_flr<=here;
				if stb='0' then nr_flr<='1';
					elsif here='1' then nr_flr<='0';
					--else here<=here;
					end if;
			end if;
	end process;
end shaft_logic;

[robocon1]

Thiếu phần khai báo component shaft trong chương trình chính.

[Feri Rocky]

Bác có thể chỉ thêm cho e phần mô phỏng ko. e chỉ chạy được xung clock .
Nếu muốn viết các xung tín hiệu khác thì viết nhw thế nào.
Em xin cảm ơn trước. mong các bác giúp đỡ

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY testbench IS
END testbench;
 
ARCHITECTURE behavior OF testbench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT MAIN
    PORT(
         CLK : IN  std_logic;
         KEEP_GOING : IN  std_logic;
         START : IN  std_logic;
         STOP_HERE : IN  std_logic;
         F : IN  std_logic_vector(4 downto 0);
         HERE : IN  std_logic;
         STB : IN  std_logic;
         FLR : OUT  std_logic_vector(4 downto 0);
         BRAKE : OUT  std_logic;
         DN : OUT  std_logic;
         UP : OUT  std_logic;
         RUN : OUT  std_logic;
         SLOW : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal KEEP_GOING : std_logic := '0';
   signal START : std_logic := '0';
   signal STOP_HERE : std_logic := '0';
   signal F : std_logic_vector(4 downto 0) := (others => '0');
   signal HERE : std_logic := '0';
   signal STB : std_logic := '0';

 	--Outputs
   signal FLR : std_logic_vector(4 downto 0);
   signal BRAKE : std_logic;
   signal DN : std_logic;
   signal UP : std_logic;
   signal RUN : std_logic;
   signal SLOW : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: MAIN PORT MAP (
          CLK => CLK,
          KEEP_GOING => KEEP_GOING,
          START => START,
          STOP_HERE => STOP_HERE,
          F => F,
          HERE => HERE,
          STB => STB,
          FLR => FLR,
          BRAKE => BRAKE,
          DN => DN,
          UP => UP,
          RUN => RUN,
          SLOW => SLOW
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for CLK_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

[Jobs]

bạn phải khai báo thêm component shaft chứ:

thêm đoạn này vào dưới phần khai báo tín hiệu nè:
component shaft
Port ( f : in STD_LOGIC_VECTOR(4 DOWNTO 0);
here : in STD_LOGIC;
stb : in STD_LOGIC;
clk : in STD_LOGIC;
flr : out STD_LOGIC_VECTOR(4 DOWNTO 0);
at_flr : out STD_LOGIC;
nr_flr : out STD_LOGIC);
end component;

ok..chúc thành công..