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jefflieu
Moderator
Lần cuối: 12-08-2018, 07:54
Joined: 30-10-2007
Nơi Cư Ngụ: Melbourne
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Tạo 2 xung từ tín hiẹu Button? (Topic in the GAL - PAL - CPLD - FPGA forum)
12-01-2013, 18:27
Tạo buffer trong chip FPGA,trễ qua LUT (Topic in the Công nghệ ASIC & Advance Techno forum)
22-03-2009, 17:40
Tạo clock 1 Hz từ clock 50MHz (Topic in the Hỗ trợ học tập forum)
29-05-2010, 22:04
Tạo Ethernet IP core cho Virtex-4 (Topic in the GAL - PAL - CPLD - FPGA forum)
06-02-2009, 09:30
30-10-2011, 22:21
Tạo task trong Quantus II (Topic in the GAL - PAL - CPLD - FPGA forum)
21-12-2012, 20:08
technology@ (member)
13-09-2012, 21:40
testbech verilog (Topic in the GAL - PAL - CPLD - FPGA forum)
16-09-2014, 07:28
thắc mắc khi bắt đầu thiết kế uart (Topic in the GAL - PAL - CPLD - FPGA forum)
22-05-2013, 07:06
Thắc mắc thân architecture! (VHDL) (Topic in the GAL - PAL - CPLD - FPGA forum)
16-07-2014, 11:19
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