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Tớ vừa mới nghỉ vacation về. Tớ sẽ gửi sớm cho các bạn Custom designer và sẽ trả lời môt số thắc mắc. -
Lần trước mình cũng bị như vậy, mày mò cũng cả mấy ngày rồi mới hiểu ra - vì vtiger mới bắt đầu xử dụng linux,Nguyên văn bởi hotelcalifor Xem bài viết
khi viết command trong bashrc -- đôi lúc viết không trúng, hay vì lý do gì ... đó khiến O/S không xử dụng new bashrd
do đó khi viết lại bashrc thì type command source .bashrc xong rồi type su trong terminal windows nếu nó có vấn
đề gì thì nó sẽ display lên.
Cách hay nhất là check lại bashrc
# Cadence stuff
cadence () {
CDS_ROOT= path ../IC61 <......................
export DD_DONT_DO_OS_LOCKS=SET
export CDS_LIC_FILE=$CDS_ROOT/share/license/license.dat <.............................
export LM_LICENSE_FILE=$CDS_ROOT/share/license/license.dat <.............................
export SPECTRE_DEFAULTS=-E
export CDS_Netlisting_Mode=Analog
export OA_HOME=path ......./IC61/oa_v22.04.0xx <.............................
export PATH=$CDS_ROOT/tools/bin:$PATH
export PATH=$CDS_ROOT/tools/dfII/bin:$PATH
export PATH=$CDS_ROOT/tools/spectre/bin:$PATH
export PATH=$CDS_ROOT/share/bin:$PATH
export PATH=$CDS_ROOT/share/cdsdoc/bin:$PATH
export PATH=$CDS_ROOT/MMSIM71/tools.lnx86/bin:$PATH ************
export PATH=$CDS_ROOT/ETS91/tools.lnx86/bin:$PATH ************
export CDS_TEST_LIBPATH=/usr/lib:/lib
} .... nhớ có em nàyLeave a comment:
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anh Rommel.de . Em đã cài xong Hspice, Design compiler và custome wave view, tuy nhiên chạy license server ok nhưng vào chạy phần mềm thi nó báo ko kiếm dc license...cái nào cũng vậy. Anh có gợi ý gì ko vậy.
Anh share cho e file synopsys.crt support cho hpice custome wave view và design compiler với. Tốt nhất a quay cái clip rồi úp lên cho khỏe mọi người đi. Thanks aLeave a comment:
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Xin chào, mình cần Synosys Custom designer ... bạn nào có up cho mình đc ko, Đặc biệt bạn nào biết ***** hoặc tạo keygen và dùng trên Windown thì chỉ mình với. Cám ơn rất nhiềuLeave a comment:
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Hi all,
Minh dang gap van de install Cadence IC 6.14 len Centos 6.0. Minh lam theo huong dan cua file dinh ke`m va theo link nay:
Best Linux to work with tools - Sonsivri
(bai viet cua Adecforever)
Minh đã cài xong Cadence IC 6.14 hot fix, rồi patch như hướng dẫn trong file dinh kem, roi source new .bashrc file. Đến step thứ 9 trong file dinh kem:
9) Now type in command window cadence (press enter)
10)Type vir (press enter)
Thi minh bi loi la: bash: cadence: command not found
Minh su dung ca license file cua ban Rommel.de & tu attach file trong bai viet tren sonsivri đều bị lỗi như vậy.
Có ai giúp đỡ mình với. Cảm ơn các bạn nhiều!Leave a comment:
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Cảm ơn bạn Kid1412_net nhiều
Theo gợi ý của bạn, mình search google và tìm ra giải pháp: disable cái Consistent Network Device Naming của fedora 15 bằng cách:
- Vào /lib/udev/rules.d/71-biosdevname.rules, uncomment dòng 15 "# GOTO=netdevicenam_end"
- Rồi khởi động lại máy
Giờ vcs chạy OK
Thanks.Leave a comment:
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@mgdaubo: Bạn cài Fedora 15 trên máy desktop hay laptop?
Nếu dùng máy desktop thì mình nghĩ nên cài lại Fedora 14 thì hơn. Bản Fedora 15 sửa đổi 1 số phần liên quan đến card mạng (từ eth0 thành em1, có thể kiểm tra = lệnh ifconfig) nên dẫn đến FlexLM ko nhận được license của mình đâu.
- Lúc debug thì nên dùng tool lmdiag (có trong SCL/linux/bin/ đó) sẽ cho kq chính xác hơn ^^Leave a comment:
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Hi các anh,
Em đang gặp vấn đề với synopsys VCS trên fedora 15:
1. Cài đặt và license như anh Rommel.de.
2. Sửa file /etc/hosts: thêm dòng 127.0.0.1 mgdaubo vào (host_name của em là mgdaubo, em dùng MAC của cổng LAN nhưng ko cắm dây mạng)
3. Chạy lmgrd -c synopsys.dat nó báo:
4. setenv SNPSLMD_LICENSE_FILE /usr/synopsys/10.9.3/synopsys.dat21:22:37 (lmgrd) -----------------------------------------------
21:22:37 (lmgrd)
21:22:37 (lmgrd)
21:22:37 (lmgrd) FLEXnet Licensing (v10.8.5.0 build 31891 i86_re3) started on mgdaubo (linux) (10/29/2011)
21:22:37 (lmgrd) Copyright (c) 1988-2006 Macrovision Europe Ltd. and/or Macrovision Corporation. All Rights Reserved.
21:22:37 (lmgrd) US Patents 5,390,297 and 5,671,412.
21:22:37 (lmgrd) World Wide Web: http://www.macrovision.com
21:22:37 (lmgrd) License file(s): /usr/synopsys/10.9.3/synopsys.dat
21:22:37 (lmgrd) lmgrd tcp-port 27000
21:22:37 (lmgrd) Starting vendor daemons ...
21:22:37 (lmgrd) Started snpslmd (internet tcp_port 48959 pid 1966)
21:22:37 (snpslmd) FLEXnet Licensing version v10.8.5.3 build 59306 i86_re3
21:22:37 (snpslmd) Synopsys Corporate Licensing (SCL) Release: version SCL_10.9.3
21:22:37 (snpslmd) Server started on mgdaubo for: SSS
21:22:37 (snpslmd) railmill railmill/ace railmill/av
21:22:37 (snpslmd) railmill/spnx rslv3d rslv3dviewer
21:22:37 (snpslmd) simwave simwave_epic spice_parser
21:22:37 (snpslmd) techviewer timemill timemill/ace
21:22:37 (snpslmd) timemill/av timemill/bdc timemill/msx
21:22:37 (snpslmd) vera_comp vera_debug vera_rtime
21:22:37 (snpslmd) vhdl_compiler vlog2e vtran
21:22:37 (snpslmd) ispLSI1K ispLSI2K ispLSI2KE
21:22:37 (snpslmd) ispLSI3K ispLSI5000S ispLSI5000SE
21:22:37 (snpslmd) ispLSI5K ispLSI6K ispLSI8K
21:22:37 (snpslmd) ispMACH4000 lsim_parser pathmill
21:22:37 (snpslmd) pathmill/dsx pathmill/pfx pathmill/sfx
21:22:37 (snpslmd) pmga powerarc powrmill
21:22:37 (snpslmd) powrmill/ace powrmill/av powrmill/msx
21:22:37 (snpslmd) primepower primepower_gui provhdl_checker
21:22:37 (snpslmd) pwga acega amga
21:22:37 (snpslmd) amps arc arc/bcx
21:22:37 (snpslmd) arc/lefdef arcviewer arcviewer/raph
21:22:37 (snpslmd) arcxl c_exe_ax c_exe_cbx
21:22:37 (snpslmd) c_exe_gx cadence chipviewer
21:22:37 (snpslmd) cmod cmod/ax cmod/cbx
21:22:37 (snpslmd) cmod/gx cmod/gxadv coreConsultant
21:22:37 (snpslmd) eX edif2e gentech
21:22:37 (snpslmd) Verilog-To-BE Vivace-Code-Generator Vivace-Core
21:22:37 (snpslmd) Vivace-Debug Vivace-Elaborator Vivace-Expert
21:22:37 (snpslmd) Vivace-Express Vivace-GUI Vivace-HDL-Analyzer
21:22:37 (snpslmd) Vivace-Model-Compiler Vivace-Pro Vivace-Simulator
21:22:37 (snpslmd) Vivace-VHDL-Analyzer WRITE XC3000
21:22:37 (snpslmd) XC4000 XC4000E XC4000EX
21:22:37 (snpslmd) XC4000L XC4000XL XC4000XLA
21:22:37 (snpslmd) XC4000XV XC5200 XC9500
21:22:37 (snpslmd) XC9500XL XC9500XV XVCSDebugger
21:22:37 (snpslmd) XVCSDebugger VPC VSP_DRIVER
21:22:37 (snpslmd) VSS-Analyzer VSS-Backplane VSS-CLI
21:22:37 (snpslmd) VSS-Cadence-Interface VSS-CompiledSim VSS-Debugger
21:22:37 (snpslmd) VSS-Falcon-Interface VSS-GateSim VSS-LAI-Models
21:22:37 (snpslmd) VSS-LMSI VSS-Lib-Tools VSS-Model-Developer
21:22:37 (snpslmd) VSS-NEC-Tran VSS-SDF-Interface VSS-SGE-Tool
21:22:37 (snpslmd) VSS-SPC VSS-Simulator VSS-SmartModels
21:22:37 (snpslmd) VSS-Tran VSS-Utilities VSS-VIP-Interface
21:22:37 (snpslmd) VSS-Verilog-PLI VSS-Wave-Display VSS-XP-Accelerator
21:22:37 (snpslmd) Verification-Token Verilog Verilog-Netlist-Writer
21:22:37 (snpslmd) Verilog-Parser TestManager TestSim
21:22:37 (snpslmd) Ultra37000 VANTIS VCSCompiler_Net
21:22:37 (snpslmd) VCSDebugger_Net VCSPostProcDebugger_Net VCSRuntime_Net
21:22:37 (snpslmd) VCSTools_Net VT_Assertions VT_AssertionsRuntime
21:22:37 (snpslmd) VT_Coverage VT_CoverageRuntime VT_Testbench
21:22:37 (snpslmd) VT_TestbenchRuntime VT_Visual VDesktop-Debug
21:22:37 (snpslmd) VDesktop-GUI VDesktop-VCDTrans VDesktop-VHDL
21:22:37 (snpslmd) VDesktop-Verilog VHDL-Analyzer VHDL-Compiler
21:22:37 (snpslmd) VHDL-Cycle-Sim VHDL-Elaborator VHDL-Event-Sim
21:22:37 (snpslmd) VHDL-Netlist-Writer VHDL-To-BE VHDL-VirSim
21:22:37 (snpslmd) VHMC-Eval VHMC-GenUnlocked VHMC-Runtime
21:22:37 (snpslmd) VIRTEX VIRTEX2 VIRTEX2P
21:22:37 (snpslmd) VIRTEXE VIRTEXEA Test-Beta-2
21:22:37 (snpslmd) Test-CA Test-Compile Test-Compile-Remodel
21:22:37 (snpslmd) Test-Compile-Share Test-Compiler Test-Compiler-Plus
21:22:37 (snpslmd) Test-Compiler-Remodel Test-Custom-Protocols Test-DFT-Top
21:22:37 (snpslmd) Test-Delay Test-Diagnosis Test-Eval
21:22:37 (snpslmd) Test-Faultsim Test-Faultsim-8L Test-Format
21:22:37 (snpslmd) Test-IDDQ Test-IEEE-Std-1149-1 Test-Library
21:22:37 (snpslmd) Test-Map Test-Mbist Test-Mbist-Algorithm
21:22:37 (snpslmd) Test-Mbist-CAM Test-Mbist-DRAM Test-Mbist-Diagnosis
21:22:37 (snpslmd) Test-Mbist-FLASH Test-Mbist-Multiport Test-RTL-Check
21:22:37 (snpslmd) Test-ScanRoute SynLib-Eval SynLib-FltTol
21:22:37 (snpslmd) SynLib-PCIbasic SynLib-Seq SynLib-VHDLSimMdl
21:22:37 (snpslmd) SynLib-VerilogSimMdl Synopsys Synopsys-Queue
21:22:37 (snpslmd) Synopsys-Release TBM-Manager-UI TBM-VSS-Check
21:22:37 (snpslmd) TBS TC-Beta TDL-Interface
21:22:37 (snpslmd) TDL-Reader TDL-Writer TRUE
21:22:37 (snpslmd) Test-ATPG Test-ATPG-30 Test-ATPG-Limited
21:22:37 (snpslmd) Test-ATPG-PRO Test-ATPG-Ultra Test-ATPG-XP
21:22:37 (snpslmd) Test-Accelerator Test-Analysis Test-Analysis-GUI
21:22:37 (snpslmd) Test-Analysis-RTL Test-BIST Test-BSDL
21:22:37 (snpslmd) Test-Beta QLOGIC Quantum38k
21:22:37 (snpslmd) RT54SXS RTL-Analyzer RTL-Analyzer-DAP
21:22:37 (snpslmd) RTL-Analyzer-Shell RTL-Analyzer-Shell-DAP RTL-Power-Analysis
21:22:37 (snpslmd) SGE-DC-Interface SGE-EDIF-Interface SGE-Tool
21:22:37 (snpslmd) SGE-VHDL-Interface SGE-Verilog-Interface SNPS-CSL
21:22:37 (snpslmd) SNPS-Keygen SNPS-MOTIVE SPARTAN
21:22:37 (snpslmd) SPARTAN2 SPARTAN2E SPARTANXL
21:22:37 (snpslmd) SYNARIO ShortCut-DC-Expert ShortCut-DC-Pro
21:22:37 (snpslmd) Shortcut-FPGA Stamp-Compiler Syn-Library-Compiler
21:22:37 (snpslmd) SynLib-ALU SynLib-AdvMath SynLib-Control
21:22:37 (snpslmd) SynLib-DSPFIR MIF-Reader MIF-Writer
21:22:37 (snpslmd) MOTIVE-PrimeTime Mentor-Interface Millennium-ATPG-EE
21:22:37 (snpslmd) Millennium-ATPG-STD Millennium-Beta Millennium-DRC
21:22:37 (snpslmd) Millennium-Eval Millennium-FS Mixed-Language
21:22:37 (snpslmd) Mixed-Paradigm ORCA2A ORCA2TB
21:22:37 (snpslmd) ORCA3C ORCA3FPSC ORCA3L
21:22:37 (snpslmd) ORCA4E Parse-Tree-Translator PhysOpt-GUI
21:22:37 (snpslmd) Power-Analysis Power-Optimization Power-Optimization-Upgrade
21:22:37 (snpslmd) PrimeTime PrimeTime-Plus Protocol-Compiler-Analysis
21:22:37 (snpslmd) Protocol-Compiler-COutput Protocol-Compiler-FML Protocol-Compiler-Synth
21:22:37 (snpslmd) Protocol-Compiler-UI Library-Compiler MACH1
21:22:37 (snpslmd) MACH2 MACH4 MACH5
21:22:37 (snpslmd) MAX3000A MAX7000 MAX7000A
21:22:37 (snpslmd) MAX7000AE MAX7000B MAX7000E
21:22:37 (snpslmd) MAX7000S MAX9000 MC-Pro
21:22:37 (snpslmd) MC-Pro-RP MC-Retime MCD
21:22:37 (snpslmd) MCE MCE-Base MCE-Eval
21:22:37 (snpslmd) MCE-Lib-ALU MCE-Lib-Arith1 MCE-Lib-Arith2
21:22:37 (snpslmd) MCE-Lib-Arith3 MCE-Lib-Logic MEMPRO
21:22:37 (snpslmd) MEMPRO-LIB MERCURY FPGA_Express-APROA-Optimizer
21:22:37 (snpslmd) FSM-Reader FSM-Writer Flash370i
21:22:37 (snpslmd) Floorplan-Management Formality Formality-E1
21:22:37 (snpslmd) Fridge-GUI Fridge-Interpolator FusionVantageLmcInterface
21:22:37 (snpslmd) GENERICVSP HDL HDL-Advisor
21:22:37 (snpslmd) HDL-Advisor-Estimator HDL-Advisor-Estimator-Package HDL-Advisor-Package
21:22:37 (snpslmd) HDL-Advisor-Shell HDL-Advisor-Shell-Estimator HDL-Advisor-Shell-Estm-Package
21:22:37 (snpslmd) HDL-Advisor-Shell-Package HDL-Compiler HighLevel-Power-Analysis
21:22:37 (snpslmd) HighLevel-Power-Optimization Key-Generator LMCSwift_Net
21:22:37 (snpslmd) LSI-Interface LSS4E Leakage-Power
21:22:37 (snpslmd) FPGA-Express-EPM7k-Optimizer FPGA-Express-EPM9k-Optimizer FPGA-Express-GAT
21:22:37 (snpslmd) FPGA-Express-ISP4000-Optimizer FPGA-Express-ISP5000-Optimizer FPGA-Express-MERCURY-Optimizer
21:22:37 (snpslmd) FPGA-Express-ORCA2-Optimizer FPGA-Express-ORCA3-Optimizer FPGA-Express-Open-Optimizer
21:22:37 (snpslmd) FPGA-Express-Synario-Optimizer FPGA-Express-VHDL-Base FPGA-Express-VHDL-Training
21:22:37 (snpslmd) FPGA-Express-VIRTEX-Optimizer FPGA-Express-VLOG-Base FPGA-Express-XC3k-Optimizer
21:22:37 (snpslmd) FPGA-Express-XC4k-Optimizer FPGA-Express-XC5k-Optimizer FPGA-Express-XC9k-Optimizer
21:22:37 (snpslmd) FPGA-Express-isp1K-Optimizer FPGA-Express-isp2K-Optimizer FPGA-Express-isp3K-Optimizer
21:22:37 (snpslmd) FPGA-Express-isp4K-Optimizer FPGA-Express-isp5K-Optimizer FPGA-Express-isp6K-Optimizer
21:22:37 (snpslmd) FPGA-Express-isp7K-Optimizer FPGA-Express-isp8K-Optimizer FPGA-HDL-Bundle
21:22:37 (snpslmd) FPGA-Library-Compiler FPGA-Option FPGA-VHDL-Bundle
21:22:37 (snpslmd) Early-Access-Technology Equation-Reader Equation-Writer
21:22:37 (snpslmd) Espresso-Reader Espresso-Writer Estm-HDL-Advisor
21:22:37 (snpslmd) Estm-HDL-Advisor-Package Eview FCII-Altera-Edition
21:22:37 (snpslmd) FLEX10K FLEX10KA FLEX10KB
21:22:37 (snpslmd) FLEX10KE FLEX6000 FLEX8000
21:22:37 (snpslmd) FPGA-Compiler FPGA-Express FPGA-Express-32OODx-Optimizer
21:22:37 (snpslmd) FPGA-Express-A1200XL-Optimizer FPGA-Express-A1400-Optimizer FPGA-Express-A3200DX-Optimizer
21:22:37 (snpslmd) FPGA-Express-A42MX-Optimizer FPGA-Express-A54SX-Optimizer FPGA-Express-APEX2-Optimizer
21:22:37 (snpslmd) FPGA-Express-APROA-Optimizer FPGA-Express-Constraint-Mgr FPGA-Express-EP20k-Optimizer
21:22:37 (snpslmd) FPGA-Express-EPF10k-Optimizer FPGA-Express-EPF6k-Optimizer FPGA-Express-EPF8k-Optimizer
21:22:37 (snpslmd) DesignWare-8051MCU DesignWare-Cardbus DesignWare-Developer-MGI
21:22:37 (snpslmd) DesignWare-Ethernet DesignWare-Foundation DesignWare-Foundation-Exp
21:22:37 (snpslmd) DesignWare-Foundation-Expert DesignWare-Foundation-Power DesignWare-Foundation-Ultra
21:22:37 (snpslmd) DesignWare-ISA-PnP DesignWare-MGI DesignWare-PCIbasic
21:22:37 (snpslmd) DesignWare-Package DesignWare-VERA Designware-Basic
21:22:37 (snpslmd) Designware-Developer Designware-FPGA-Basic E5
21:22:37 (snpslmd) E502 E505 E520
21:22:37 (snpslmd) ECL-Compiler ECO-Compiler EDIF-Netlist-Read-DC
21:22:37 (snpslmd) EDIF-Netlist-Write-DC EDIF-Netlist-Writer EDIF-Reader
21:22:37 (snpslmd) EDIF-Schematic-Writer EXCALIBUR_ARM EXCALIBUR_MIPS
21:22:37 (snpslmd) DEMO DIRECTMEM DS-Schem-Gen
21:22:37 (snpslmd) DS-Schem-Gen-Estimator-Pa DS-Schem-Gen-Estimator-Package DS-Schem-Gen-Package
21:22:37 (snpslmd) DS-Verinet DS-Verinet-Estimator-Pack DS-Verinet-Estimator-Package
21:22:37 (snpslmd) DS-Verinet-Package DS-Vhdlnet DS-Vhdlnet-Estimator-Pack
21:22:37 (snpslmd) DS-Vhdlnet-Estimator-Package DS-Vhdlnet-Package DW-Developer
21:22:37 (snpslmd) DW-IP-Consultant DW-IP-Developer Delta39k
21:22:37 (snpslmd) Design-Analyzer Design-Analyzer-DAP Design-Budgeting
21:22:37 (snpslmd) Design-Compiler Design-Estimator Design-Estimator-FPI
21:22:37 (snpslmd) Design-Vision DesignSource DesignSource-Estimator-Package
21:22:37 (snpslmd) DesignSource-Package DesignTime DesignWare
21:22:37 (snpslmd) COSSAP_vsiccg_vcs COSSAP_vsiccg_vlgxl COSSAP_vsivcg
21:22:37 (snpslmd) COSSAP_vsivcg_vlgxl COSSAP_xdcg COSSAP_xvcg
21:22:37 (snpslmd) COSSAP_xvsi CTV-Interface CYPRESS
21:22:37 (snpslmd) CmView CoverMeter Cyclone-Code-Generator
21:22:37 (snpslmd) Cyclone-Core Cyclone-Elaborator Cyclone-GUI
21:22:37 (snpslmd) Cyclone-HDL-Analyzer Cyclone-Simulator Cyclone-VHDL-Analyzer
21:22:37 (snpslmd) Cyclone-cosim DATAIO DC-Beta
21:22:37 (snpslmd) DC-Cadence-Interface DC-Expert DC-Falcon-Interface
21:22:37 (snpslmd) DC-Layout-Interface DC-Min-Area-Retime DC-SDF-Interface
21:22:37 (snpslmd) DC-Ultra-Features DC-Ultra-Opt DCM-Delay-Calculation
21:22:37 (snpslmd) COSSAP_dect COSSAP_dvb COSSAP_ecc
21:22:37 (snpslmd) COSSAP_gsmdve COSSAP_gsmdve_utils COSSAP_gsmefrsc
21:22:37 (snpslmd) COSSAP_gsmeq COSSAP_gsmfrcc COSSAP_gsmfrsc
21:22:37 (snpslmd) COSSAP_gsmhrcc COSSAP_gsmhrsc COSSAP_gsmphy
21:22:37 (snpslmd) COSSAP_is136 COSSAP_is95 COSSAP_matlab
21:22:37 (snpslmd) COSSAP_mfd COSSAP_mpeg2 COSSAP_pdc
21:22:37 (snpslmd) COSSAP_qed COSSAP_sds COSSAP_srcfd
21:22:37 (snpslmd) COSSAP_vcg_generic COSSAP_vcg_synopsys COSSAP_vcg_vantage
21:22:37 (snpslmd) COSSAP_vdefcg COSSAP_vdefcg_vlgxl COSSAP_vsiccg
21:22:37 (snpslmd) COSSAP_vsiccg_cyc COSSAP_vsiccg_mti COSSAP_vsiccg_mtivlg
21:22:37 (snpslmd) COOLRUNNER COOLRUNNER2 COSSAP_adpcm
21:22:37 (snpslmd) COSSAP_arm COSSAP_bde COSSAP_celp
21:22:37 (snpslmd) COSSAP_chart COSSAP_cw_filter_hdl COSSAP_cw_filter_sds
21:22:37 (snpslmd) COSSAP_dab COSSAP_dcg_ad21020 COSSAP_dcg_ansic
21:22:37 (snpslmd) COSSAP_dcg_ariel32c COSSAP_dcg_fe COSSAP_dcg_gc
21:22:37 (snpslmd) COSSAP_dcg_krc COSSAP_dcg_lsic30s COSSAP_dcg_m96000
21:22:37 (snpslmd) COSSAP_dcg_mp COSSAP_ddk_arm COSSAP_ddk_devlp
21:22:37 (snpslmd) COSSAP_ddk_dsp1610 COSSAP_ddk_hawk COSSAP_ddk_nec
21:22:37 (snpslmd) COSSAP_ddk_oak COSSAP_ddk_pine COSSAP_ddk_ssp16xx
21:22:37 (snpslmd) COSSAP_ddk_tic5x COSSAP_ddk_tic5xx BC-FPGA-HDL
21:22:37 (snpslmd) BC-FPGA-VHDL BC-HDL BC-Schedule
21:22:37 (snpslmd) BC-VHDL BOA-BRT Behavioral-Analyzer
21:22:37 (snpslmd) Behavioral-Compiler CA-CP-Advanced CA-CP-Basic
21:22:37 (snpslmd) CA-CP-Standard CA-Chip-Edit CA-Foundation
21:22:37 (snpslmd) CA-Frame CA-Hier-Timer CA-Optimization
21:22:37 (snpslmd) CA-Timer CA-Utils CD-Compiled-Lib-Gen
21:22:37 (snpslmd) CD-Compiled-Sys-Gen CD-GDI CD-GDII-Link
21:22:37 (snpslmd) CD-MSSC-Cross-Probe CD-MSSC-Netlist CD-Model-Developer
21:22:37 (snpslmd) CD-Present-Builder CD-Present-Layer-Gen CD-REX
21:22:37 (snpslmd) CD-Vhdlgen-GUI CD-Vhdlgen-Gen A3200DX
21:22:37 (snpslmd) A42MX A500K A54SX
21:22:37 (snpslmd) A54SXA A7 ACEX1K
21:22:37 (snpslmd) ACS ACT2-1200XL ACT3
21:22:37 (snpslmd) ALTGEN1 ALTGEN2 APEX20K
21:22:37 (snpslmd) APEX20KC APEX20KE APEXII
21:22:37 (snpslmd) ARKOS-A ARKOS-B ARKOS-C
21:22:37 (snpslmd) ARKOS-D ARKOS-E ARKOS-Ice
21:22:37 (snpslmd) ARKOS-Mcomp ARKOS-Rtlcomp ARKOS-Scomp
21:22:37 (snpslmd) ARKOS-Simul ARM7TDMI ATMEL
21:22:37 (snpslmd) ATMWB_ATMLAYER ATMWB_UTOPIA
21:22:37 (snpslmd)
21:22:37 (snpslmd) Licenses are case sensitive for TE_CATS
21:22:37 (snpslmd)
21:22:37 (snpslmd) EXTERNAL FILTERS are OFF
21:22:37 (lmgrd) snpslmd using TCP-port 48959
21:22:37 (snpslmd) Serving features for the following vendor names:
snpslmd CADABRA EPIC ISE-TCADd TE_CATS adalmd anagram archprod avantd chrysalisd everest hscd innologd la_dmon leda metasoftd nassd numeritchd saber_dmn sandwork sigmacd slat snpsOEM1 snpsOEM2 snpsOEM3 snpsOEM4 snpsOEM5 snpsOEM6 snpsOEM7 snpsOEM8 snpsOEM9 ssilmd synopsysd tmald vcsd
21:22:38 (snpslmd) ------------------------------------------------------------------
21:22:38 (snpslmd) Checking the integrity of the license file....
21:22:38 (snpslmd) Valid SSS feature found.
21:22:38 (snpslmd) The feature is needed to enable the other keys in your license file.
21:22:38 (snpslmd) ------------------------------------------------------------------
21:24:19 (snpslmd) TCP_NODELAY NOT enabled
setenv VCS_HOME /usr/synopsys/D-2010.06-SP1
set PATH=/usr/synopsys/D-2010.06-SP1/bin:$PATH
5. Chạy: /usr/synopsys/D-2010.06-SP1/bin/vcs -R -debug_pp testbench.v --> kết quả:
Warning-[LNX_OS_VERUN] Unsupported Linux version
Linux version 'Fedora release 15 (Lovelock)' is not supported on 'i686'
officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE
to linux or suse32 to override.
Please refer to release notes for information on supported platforms.
Chronologic VCS (TM)
Version D-2010.06-SP1 -- Sun Oct 30 01:03:44 2011
Copyright (c) 1991-2010 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Invalid host in license file.
Not Authorized to run from this host.
None of the nodelocked licenses in the license file match this host.
Rerun from the correct host.
Failed to obtain license...
Note: Use +vcs+lic+wait ( or -licwait <minute> or -licqueue in Unified Use Model ) to queue for license
CPU time: .031 seconds to compile
Đến đây thì bó chiếu, mò mẫm cả ngày ko xong. Xin nhờ các anh nhiều kinh nghiệm chỉ giáo.
Thanks in advance.Last edited by mgdaubo; 30-10-2011, 02:32.Leave a comment:
-
có video hướng dẫn trong đây:
Synopsys Design Compiler 2008.09 (With installation movie)
Part-1 :: Synopsys_DC.rar.001
Part-2 :: Synopsys_DC.rar.002
Synopsys - All Software here - SonsivriLeave a comment:
-
hi guys.
Does anyone access to mentor graphics download server. I need mentor Vista (A Complete TLM 2.0-based Solution). ThanksLeave a comment:
-
Hello I am in need of this
Advanced Algorithm Implementation with Synplify DSP labs
Synplify DSP
CAN ANYONE ACQUIRE ITS TRAINNING LABSLeave a comment:
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hi Rommel.de
I have a cẻtain isue:
I have sentaurus lithography E_2010 and already installed it on windows.
I wonder how can we run it?
the license doesn't include the feature of sentaurus lithography.
when i installed and tried to run it said:
missing the feature S-LITHO_EVA.
so i think we have to modify the src file to generate the correct license.
please may you help for this issue?
thanks a lot in advanceLeave a comment:
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hi Rommel.de
I have a /question about technology files. where can I find technology library (specially TSMC) for Design compiler and IC compiler? How can I use them.
thanks Rommel.deLeave a comment:
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