Tweet
Help!!! Lỗi trong tạo FSM 1Hz từ clock 50Mhz trong VHDL
Code em viết phía dưới các bác giúp em cái:
Sao nó cứ báo warning không?
Dưới đây là bài em làm:
--Ck_50Mhz_1Hz:
--FSM_BCD:
--FSM_BCD_1Hz:
Các bác giúp dùm e nha.
Sao nó cứ báo warning không?
Code:
WARNING:Xst:647 - Input <Ck_50Mhz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1305 - Output <Ck_1Hz> is never assigned. Tied to value 0. WARNING:Xst:1293 - FF/Latch <FFd1> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <FFd2> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <FFd3> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <FFd4> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1290 - Hierarchical block <khoi_xung> is unconnected in block <fsm_bcd_1hz>. It will be removed from the design. WARNING:Xst:1293 - FF/Latch <FSM_FFd4> has a constant value of 0 in block <FSM_0-parent>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <FSM_FFd3> has a constant value of 0 in block <FSM_0-parent>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <FSM_FFd2> has a constant value of 0 in block <FSM_0-parent>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <FSM_FFd1> has a constant value of 0 in block <FSM_0-parent>. This FF/Latch will be trimmed during the optimization process.
--Ck_50Mhz_1Hz:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ck_50Mhz_1Hz is
port
( Ck_50Mhz : in std_logic;
Ck_1Hz : out std_logic
);
end Ck_50Mhz_1Hz;
architecture behavioral of Ck_50Mhz_1Hz is
begin
process (Ck_50Mhz)
variable count : integer range 0 to 25000000;
variable tg : std_logic:='0';
begin
count :=0;
if rising_edge (Ck_50Mhz) then
if count = 25000000 then
count := 0;
tg := not(tg);
Ck_1Hz <= tg;
else count := count +1;
end if;
end if;
end process;
end behavioral;
Code:
library IEEE;
use ieee.std_logic_1164.all;
entity FSM_BCD is
port
( clk : in std_logic;
res : in std_logic;
out_cnt : out std_logic_vector (3 downto 0)
);
end FSM_BCD;
architecture beh of FSM_BCD IS
type state_fsm is ( state0, state1, state2, state3,
state4, state5, state6, state7,
state8, state9, state10, state11,
state12, state13, state14, state15);
signal pr_state, nx_state: state_fsm;
begin --beh;
sync : process (clk, res)
begin
if(res='1') then pr_state <= state0;
elsif rising_edge(clk) then
pr_state <= nx_state;
end if;
end process sync;
comb : process (pr_state)
begin
case (pr_state) is
when state0 => nx_state <= state1;
out_cnt <= B"0000";
when state1 => nx_state <= state2;
out_cnt <= B"0001";
when state2 => nx_state <= state3;
out_cnt <= B"0010";
when state3 => nx_state <= state4;
out_cnt <= B"0011";
when state4 => nx_state <= state5;
out_cnt <= B"0100";
when state5 => nx_state <= state6;
out_cnt <= B"0101";
when state6 => nx_state <= state7;
out_cnt <= B"0110";
when state7 => nx_state <= state8;
out_cnt <= B"0111";
when state8 => nx_state <= state9;
out_cnt <= B"1000";
when state9 => nx_state <= state10;
out_cnt <= B"1001";
when state10 => nx_state <= state11;
out_cnt <= B"1010";
when state11 => nx_state <= state12;
out_cnt <= B"1011";
when state12 => nx_state <= state13;
out_cnt <= B"1100";
when state13 => nx_state <= state14;
out_cnt <= B"1101";
when state14 => nx_state <= state15;
out_cnt <= B"1110";
when state15 => nx_state <= state0;
out_cnt <= B"1111";
when others =>null;
end case;
end process comb;
end beh;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fsm_bcd_1hz is
port
( clk_50Mhz : in std_logic;
reset : in std_logic;
outs :out std_logic_vector (3 downto 0)
);
end fsm_bcd_1hz;
architecture beha of fsm_bcd_1hz is
component FSM_BCD
port
( clk : in std_logic;
res : in std_logic;
out_cnt : out std_logic_vector (3 downto 0)
);
end component;
component Ck_50Mhz_1Hz
port
( Ck_50Mhz : in std_logic;
Ck_1Hz : out std_logic
);
end component;
signal clks :std_logic;
BEGIN
khoi_xung: Ck_50Mhz_1Hz
port map
( Ck_50Mhz => clk_50Mhz,
Ck_1Hz => clks
);
khoi_fsms : FSM_BCD
port map
( clk => clks,
res =>reset,
out_cnt => outs
);
end beha;
Attached Files
Comment